1. Field of the Invention
The present invention relates to a PLL circuit, and particularly to a PLL circuit provided with a voltage controlled oscillator (VCO) having a low gain input and a high gain input.
2. Description of Related Art
In recent years, a PLL (Phase Locked Loop) circuit is often used as an oscillator circuit mounted on a semiconductor device. A PLL circuit controls an oscillating frequency of an output signal so that phases of a reference signal and the output signal synchronize.
FIG. 12 is a block diagram illustrating a PLL circuit disclosed in U.S. Pat. No. 6,680,632. In FIG. 12, a PLL circuit 100 includes dividers 102 and 112, a phase comparator 104, a charge pump circuit 106, a low pass filter 108, a control circuit 130 provided with buffers 114 and 116, and a voltage controlled oscillator (VCO) 110.
The phase comparator 104 compares a signal obtained by dividing a frequency of a reference signal (REF) by the divider 102 with a signal obtained by dividing a frequency of an output signal (CLK) of the PLL circuit 100 by the divider 112, and then outputs a signal for controlling the charge pump circuit 106. The charge pump circuit 106 outputs a current controlled to be in an inflow direction or an outflow direction according to the output signal of the phase comparator 104. The low pass filter 108 inputs the signal from the charge pump circuit, and removes high frequency noise included in the signal. The signal with removed high frequency noise is output to a low gain input of the voltage controlled oscillator 110. The signal with removed high frequency noise is output to a high gain input of the voltage controlled oscillator 110 via the control circuit 130 which is provided with the buffer 114 and the filter 116.
The buffer 114 compares an output of the low pass filter 108 with a MID_VCO signal, and controls so that the output of the low pass filter 108 is to be the same as the MID_VCO signal. The voltage controlled oscillator 110 of the PLL circuit 100 can operate simultaneously in low gain mode and high gain mode.
FIG. 14 is a block diagram illustrating a PLL circuit disclosed in Japanese Unexamined Patent Application Publication No. 2008-48320. As illustrated in FIG. 14, the PLL circuit includes dividers 210, 211, and 221, a phase comparator 212, a first charge pump circuit 213, an integrating filter 214, a first voltage-current converting circuit 215, a second charge pump circuit 216, a ripple filter 217, a second voltage-current converting circuit 218, a reference voltage generation circuit 219, and a current controlled oscillator 220.
The PLL circuit illustrated in FIG. 14 divides a frequency of a reference signal Fin by the divider 210. Further, the output signal Fout is divided with the divider 211. Then, a phase of an output signal of the divider 210 is compared with that of the divider 211 by the phase comparator 212. Then, the phase comparator 212 generates a voltage-up signal UP and a voltage-down signal DN based on the phase difference therebetween. The first charge pump circuit 213 and the second charge pump circuit 216 output a current based on a difference between the pulse width of the voltage-up signal UP and the pulse width of the voltage-down signal DN.
The current output from the first charge pump circuit 213 is converted into voltage by a capacitor C1 of the integrating filter 214. At this time, the integrating filter 214 removes a high frequency noise generated by the operation of the first charge pump circuit 213.
On the other hand, the current output from the second charge pump circuit 216 is converted into voltage via the ripple filter 217. The ripple filter 217 reduces ripple noise. Then, the voltage with reduced level of the ripple noise is input to the second voltage-current converting circuit 218. The second voltage-current converting circuit 218 compares the reference voltage generated in the reference voltage generation circuit 219 with the voltage input via the ripple filter 217. Then, the second voltage-current converting circuit 218 outputs a current according to the comparison result of the two voltages.
The output of the first voltage-current converting circuit 215 and the output of the second voltage-current converting circuit 218 are connected to each other, and then input to the current controlled oscillator 220. That is, the current input to the current controlled oscillator 220 is the addition of the output current of the first voltage-current converting circuit 215 and the output current of the voltage-current converting circuit 218. The current controlled oscillator 220 controls the oscillation frequency of the output signal based on the current generated according to such voltage. Then, the divider 221 divides the frequency of the output signal of the current controlled oscillator 220 to generate the output signal Fout. Further, the output Fout is fed back, and the phases of the output signal Fout and the reference signal Fin are compared. Then the phase of the output signal Fout is synchronized with the phase of the reference signal Fin.
Therefore, the PLL circuit illustrated in FIG. 14 can operate the ripple filter 217 and the integrating filter 214 with different currents. Thus, the current supplied to the integrating filter 214 can be smaller than the current supplied to the ripple filter 217. Moreover, the capacitance value of the capacitor C1 of the integrating filter can be reduced based on the ratio α between the current supplied to the integrating filter 214 and the ripple filter 217.